Open andrewandrepowell opened 1 year ago
Hello!
As the title states, is there a way to configure the VHDL Generator to generate VHDL with entity instantiations (e.g. ff_inst : entity ex_lib.ff(rtl)), instead of component instantiations (e.g. ff_inst : ff)?
ff_inst : entity ex_lib.ff(rtl)
ff_inst : ff
Hi Andrew,
Currently only component instantiations are created in VHDL generation. I'll mark this one as a feature request and we'll add the option later.
Hello!
As the title states, is there a way to configure the VHDL Generator to generate VHDL with entity instantiations (e.g.
ff_inst : entity ex_lib.ff(rtl)
), instead of component instantiations (e.g.ff_inst : ff
)?