VHDL generation problems

[DenizzzGuzell]

Hi, module instantiations using hierarchy named "add new HW design" can cause problems on VHDL generations. Generated verilogs incluedes module hierarchy interface signals etc. but VHDL is just empty only port signals included.

[epekkar]

The VHDL and Verilog generator work differently here by design. The VHDL generator will generate the hierarchy if run in the HW Design view.

[DenizzzGuzell]

Thank you.