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kactus2 / kactus2dev

Kactus2 is a graphical EDA tool based on the IP-XACT standard.
https://research.tuni.fi/system-on-chip/tools/
GNU General Public License v2.0
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After generating VHDL lib. collapses #89

Closed DenizzzGuzell closed 7 months ago

DenizzzGuzell commented 9 months ago

Hi, error free library of mine was creating documents, verilog files etc. When I tried to generate VHDL all of the bus interfaces showing error and after I fixing and saving it, refresing library makes obsolete interfaces. Currently I am generating new library file from zero and there is not any error. Running VHDL brokes some sort of things in library I assume.

hagantsa commented 7 months ago

Hi,

Could you describe the problem a bit more in-depth? What kinds of errors did you get after trying to generate VHDL?

DenizzzGuzell commented 7 months ago

Hello, I tried the trigger this issue again to give you more spesific detail but I could not. It was basically using VHDL generation made whole library throw errors and not work neither documentation nor verilog generation. For now I am closing this issue. I will reopen it if I do trigger it again.

Thank you.