Closed DenizzzGuzell closed 7 months ago
Hi,
Could you describe the problem a bit more in-depth? What kinds of errors did you get after trying to generate VHDL?
Hello, I tried the trigger this issue again to give you more spesific detail but I could not. It was basically using VHDL generation made whole library throw errors and not work neither documentation nor verilog generation. For now I am closing this issue. I will reopen it if I do trigger it again.
Thank you.
Hi, error free library of mine was creating documents, verilog files etc. When I tried to generate VHDL all of the bus interfaces showing error and after I fixing and saving it, refresing library makes obsolete interfaces. Currently I am generating new library file from zero and there is not any error. Running VHDL brokes some sort of things in library I assume.