Verilog: is there a good reason mal has not been implemented?

[peepo]

likely beyond my skill set, but would like to work through project, cookbook style, once available...

[dubek]

Verilog: is there a good reason mal has not been implemented?

It's because no one has submitted an implementation PR yet :-)

Note that even to implement mal step0, you must implement a wrapper so that input from terminal can be fed into the Verilog "program", and the output can be displayed back in the terminal.

Good luck!