Some questions about Gigatron TTL.circ.

[KrRang]

Hello, I'm trying to implement an actual Gigatron in Logisim with your Gigatron TTL.circ!

First of all, I was amazed at the excellent implementation of the real Gigatron on Logisim. I used Gigatron TTL.circ because I wanted to create a similar environment in Gigatron as much as possible, and I have some questions about the circuit.

i) Which version of Logisim or Logisim-Evolution or Logisim-Evolution HC did these files come from?

• If you look at the image, it's like HC Edition, where the circuit was actually the most intact, and the rest of the versions were largely broken.

ii) If you look at the dataSheet on Gigatron, the top 8 bits of ROM go to IR and the bottom 8 bits to DR, but in the Logisim file, it was implemented backwards, is it intended?

iii) Have you tried uploading the actual Gigatron ROM file to the ROM of Gigatron TTL.circ?

• VGA is not implemented in this file, so I've tried implementing VGA circuits on my own, but there are a lot of bugs.
• In addition, ST(Y,Xpp) does not work properly in Logisim RAM, so D flip-flop(with CLK1) is connected to the address to implement address per clock ==> R/W behavior like Gigatron.

The Logisim version I'm currently using is the HC Edition(v5.0.3) Logisim-Evolution-HC which is the most progressive and has many different options. It's been a while, but can I share my progress if I continue this interesting project and there's an improvement?

[kara-abdelaziz]

Hello, very happy for you to give a try to Gigatron. For me, it is an amazing hardware project, and I am happy to help.

i. Gigatron TTL.circ was designed using the original Carl Bruch Logisim, the images shown in hackaday page are more explicit, you probably find more information there. I do also have a personal website where the project is more detailed (link). I am sure it is not directly compatible with Logisim evolution. I can't confirm for Logisim evolution HC, I don't know.

ii. We can see in the schematics below that the first 8 bits (DQ0 - DQ7) go to IR and the last 8 bits (DQ8 - DQ15) go register D. And in logisim they follow the same order, you can check that in logisim by inspecting inside the ROM circuit.

iii. I didn't try the original frameware of Gigatron in the Logisim similation, because you need some sort of conversion from binary format to logisim memory file format. It is not difficult by using maybe a small Python script.

• The VGA was not implemented due to the original Logisim lack of a VGA output component.
• For the instructions ST(Y,Xpp) I don't really remember what was exactly the problem. but I think if you are not intended to make it works on the original hardware, it is Ok to use it in simulation.

Of course you can share your progress. And better than that, I need to put a permissive open source license to the project, to allow everyone the possibility to use it what everthey want.