Closed karplus closed 9 years ago
Original comment by kevin_karplus (Bitbucket: kevin_karplus, ).
Done. Prescale (loading PIT0) is still limited to a byte, but this provides 2^40 bus cycles per interrupt which is over 8.48 hours, even on Teensy 3.1
Changing communication protocol to allow multiple bytes could extend to 2^64 bus cycles.
Original report by kevin_karplus (Bitbucket: kevin_karplus, ).
Change all ARM implementations to use PIT 0 and PIT 1 for both timestamps and periodic interrupts.