Clock speed not being used correctly on Teensy 3.2

[karplus]

Original report by kevin_karplus (Bitbucket: kevin_karplus, ).

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I've just replicated the behavior I was experiencing while collecting data for the aliasing lab. The time measurements that were collected for the graphs included in my lab report are absolutely incorrect - and I was aware of that when I submitted the paper. In my confusion I did not realize that the problem originated from a compiler setting used to compile the PteroDAQ firmware.

Here is the protocol to replicate my results:

(Tools used: Teensyduino 1.34, Arduino 1.6.12, Python 3.4.4, and a Teensy 3.2)

• In the Arduino IDE, set the 'CPU Speed' option to '96 MHz (overclock)' (this is apparently the default setting for the 3.2 board)
• Compile and upload the v0.2b1 PteroDAQ firmware.
• Use the circuit from Lab 3.
• Input a 20Hz sine.
• View the signal in PteroDAQ using 20Hz sampling.
• There should (incorrectly) be more than 1 sample per period.

I was able to fix the problem by configuring the 'CPU Speed' option to '72 MHz' and reprogramming the Teensy.

I hope this helps, Christian Riegels

[karplus]

Original comment by kevin_karplus (Bitbucket: kevin_karplus, ).

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The bug is confirmed. Currently the Teensy boards do not report their clock speeds in the model command. Changes will not be trivial, as the model command for ATMega boards reports clock speed as 2 bytes in kHz, and the 96MHz clock for Teensy 3.1/3.2 overclocked wouldn't fit in 2 bytes.

Probably need to change the model command and model.c to use more bytes for the clock speed, then change boards.py to understand the new model command and use it on the various boards.

[karplus]

Original comment by kevin_karplus (Bitbucket: kevin_karplus, ).

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Should be fixed by the changes in the pull request made by Juan Huerta.

[karplus]

Original comment by kevin_karplus (Bitbucket: kevin_karplus, ).

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I believe that Juan's changes fix this. I should probably confirm independently.