fpic 32 bit out of GPR registers

[GoogleCodeExporter]

This code does not build with 32 bit fpic

#if defined(__APPLE__) || defined(__x86_64__) || defined(__llvm__)
#define OMITFP
#else
#define OMITFP __attribute__((optimize("omit-frame-pointer")))
#endif

void OMITFP I422ToRGB24Row_SSSE3(const uint8* y_buf,
                                 const uint8* u_buf,
                                 const uint8* v_buf,
                                 uint8* dst_rgb24,
                                 int width) {
  asm volatile (
    "movdqa    %[kShuffleMaskARGBToRGB24_0],%%xmm5 \n"
    "movdqa    %[kShuffleMaskARGBToRGB24],%%xmm6   \n"
    "sub       %[u_buf],%[v_buf]               \n"
    "pxor      %%xmm4,%%xmm4                   \n"
    LABELALIGN
  "1:                                          \n"
    READYUV422
    YUVTORGB
    "punpcklbw %%xmm1,%%xmm0                   \n"
    "punpcklbw %%xmm2,%%xmm2                   \n"
    "movdqa    %%xmm0,%%xmm1                   \n"
    "punpcklwd %%xmm2,%%xmm0                   \n"
    "punpckhwd %%xmm2,%%xmm1                   \n"
    "pshufb    %%xmm5,%%xmm0                   \n"
    "pshufb    %%xmm6,%%xmm1                   \n"
    "palignr   $0xc,%%xmm0,%%xmm1              \n"
    "movq      %%xmm0," MEMACCESS([dst_rgb24]) "\n"
    "movdqu    %%xmm1," MEMACCESS2(0x8,[dst_rgb24]) "\n"
    "lea       " MEMLEA(0x18,[dst_rgb24]) ",%[dst_rgb24] \n"
    "sub       $0x8,%[width]                   \n"
    "jg        1b                              \n"
  : [y_buf]"+r"(y_buf),    // %[y_buf]
    [u_buf]"+r"(u_buf),    // %[u_buf]
    [v_buf]"+r"(v_buf),    // %[v_buf]
    [dst_rgb24]"+r"(dst_rgb24),  // %[dst_rgb24]
    [width]"+rm"(width)    // %[width]
  : [kYuvConstants]"r"(&kYuvConstants.kUVToB),
    [kShuffleMaskARGBToRGB24_0]"m"(kShuffleMaskARGBToRGB24_0),
    [kShuffleMaskARGBToRGB24]"m"(kShuffleMaskARGBToRGB24)
  : "memory", "cc"
#if defined(__native_client__) && defined(__x86_64__)
    , "r14"
#endif
#if defined(__SSE2__)
    , "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6"
#endif
  );
}

void OMITFP I422ToRAWRow_SSSE3(const uint8* y_buf,
                               const uint8* u_buf,
                               const uint8* v_buf,
                               uint8* dst_raw,
                               int width) {
  asm volatile (
    "movdqa    %[kShuffleMaskARGBToRAW_0],%%xmm5 \n"
    "movdqa    %[kShuffleMaskARGBToRAW],%%xmm6   \n"
    "sub       %[u_buf],%[v_buf]               \n"
    "pxor      %%xmm4,%%xmm4                   \n"
    LABELALIGN
  "1:                                          \n"
    READYUV422
    YUVTORGB
    "punpcklbw %%xmm1,%%xmm0                   \n"
    "punpcklbw %%xmm2,%%xmm2                   \n"
    "movdqa    %%xmm0,%%xmm1                   \n"
    "punpcklwd %%xmm2,%%xmm0                   \n"
    "punpckhwd %%xmm2,%%xmm1                   \n"
    "pshufb    %%xmm5,%%xmm0                   \n"
    "pshufb    %%xmm6,%%xmm1                   \n"
    "palignr   $0xc,%%xmm0,%%xmm1              \n"
    "movq      %%xmm0," MEMACCESS([dst_raw]) " \n"
    "movdqu    %%xmm1," MEMACCESS2(0x8,[dst_raw]) "\n"
    "lea       " MEMLEA(0x18,[dst_raw]) ",%[dst_raw] \n"
    "sub       $0x8,%[width]                   \n"
    "jg        1b                              \n"
  : [y_buf]"+r"(y_buf),    // %[y_buf]
    [u_buf]"+r"(u_buf),    // %[u_buf]
    [v_buf]"+r"(v_buf),    // %[v_buf]
    [dst_raw]"+r"(dst_raw),  // %[dst_raw]
    [width]"+rm"(width)    // %[width]
  : [kYuvConstants]"r"(&kYuvConstants.kUVToB),
    [kShuffleMaskARGBToRAW_0]"m"(kShuffleMaskARGBToRAW_0),
    [kShuffleMaskARGBToRAW]"m"(kShuffleMaskARGBToRAW)
  : "memory", "cc"
#if defined(__native_client__) && defined(__x86_64__)
    , "r14"
#endif
#if defined(__SSE2__)
    , "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6"
#endif
  );
}

Original issue reported on code.google.com by fbarch...@google.com on 30 Dec 2014 at 4:11

[GoogleCodeExporter]

Build 32 bit on Mac, which uses fpic

tools/clang/scripts/update.sh
GYP_DEFINES='clang=1 target_arch=ia32' ./gyp_libyuv -f ninja --depth=. 
libyuv_test.gyp
ninja -j10 -C out/Debug
ninja -j10 -C out/Release

using "m" instead produces
../../source/row_posix.cc:1702:6: error: ambiguous instructions require an 
explicit suffix (could be 'subb', 'subw', 'subl', or 'subq')
    "sub       $0x8,%[width]                   \n"
     ^

Original comment by fbarch...@google.com on 30 Dec 2014 at 6:53

[GoogleCodeExporter]

64 bit generates this for shufflers:

_I422ToRGB24Row_SSSE3:
0000000000001020    pushq   %rbp
0000000000001021    movq    %rsp, %rbp
0000000000001024    movl    %r8d, -0x4(%rbp)
0000000000001028    leaq    __ZN6libyuv13kYuvConstantsE(%rip), %rax
000000000000102f    movdqa  __ZN6libyuv25kShuffleMaskARGBToRGB24_0E(%rip), %xmm5
0000000000001037    movdqa  __ZN6libyuv23kShuffleMaskARGBToRGB24E(%rip), %xmm6

while this is the 32 bit version
_I422ToRGB24Row_SSSE3:
000011b0    pushl   %ebp
000011b1    movl    %esp, %ebp
000011b3    pushl   %ebx
000011b4    pushl   %edi
000011b5    pushl   %esi
000011b6    pushl   %eax
000011b7    calll   0x11bc
000011bc    popl    %eax
000011bd    movl    0x8(%ebp), %ecx
000011c0    movl    0xc(%ebp), %edx
000011c3    movl    0x10(%ebp), %esi
000011c6    movl    0x14(%ebp), %edi
000011c9    movl    0x18(%ebp), %ebx
000011cc    movl    %ebx, -0x10(%ebp)
000011cf    leal    __ZN6libyuv13kYuvConstantsE-4540(%eax), %ebx
000011d5    movdqa  __ZN6libyuv25kShuffleMaskARGBToRGB24_0E-4540(%eax), %xmm5
000011dd    movdqa  __ZN6libyuv23kShuffleMaskARGBToRGB24E-4540(%eax), %xmm6

Original comment by fbarch...@google.com on 30 Dec 2014 at 10:42

• Changed state: Accepted

[GoogleCodeExporter]

Work around in place, marking as fixed but with todo.

Original comment by fbarch...@google.com on 5 Jan 2015 at 6:36

• Changed state: Fixed