L1 Data Cache: 32KB, 8-way set associative, 64 Byte cache line size
L2 Unified Cache: 256KB, 8-way set associative, 64 Byte cache line size
L3 Unified Cache: up to 8MB, 64-way set associative, 64 Byte cache line size
Instruction TLB(4KB Pages): 64 entries per thread(128 per core), 4-way set associative
Data TLB(4KB Pages): DTLB0->64 entries, 4-way set associative
Instruction TLB(Large Pages): 7 entries per thread, fully associative
Data TLB(Larger Pages): DTLB0->32 entries, 4-way set associative
Second-Level Unified TLB(4KB Pages): STB->512 entries, 4-way set associative
Store Buffer: 32 entries
Write Coming(WC) Buffer: 无
The processor always reads a cache line from system memory beginning on a 64-
byte boundary. (A 64-byte aligned cache line begins at an address with its 6 least-significant bits clear.)
A cache line can be filled from memory with a 8-transfer burst transaction. The caches do not support partially-filled cache
lines, so caching even a single doubleword requires caching an entire line.
The TLBs store the most recently used page-directory and page-table entries. They speed up memory accesses when paging
is enabled by reducing the number of memory accesses that are required to read the page tables stored in system memory.
Intel 64和IA-32架构支持cache，translation lookaside buffers(TLBs) 以及Store buffer。
下面以Intel I7为例介绍各项参数。
The processor always reads a cache line from system memory beginning on a 64- byte boundary. (A 64-byte aligned cache line begins at an address with its 6 least-significant bits clear.)
处理器以64Byte边界来从内存读取一条缓存行，即从低6位清零的地址开始实现64Byte对齐的缓存行。
A cache line can be filled from memory with a 8-transfer burst transaction. The caches do not support partially-filled cache lines, so caching even a single doubleword requires caching an entire line.
一条缓存行可以是从突发事务(连续传输多个地址)的8次传输填充。缓存行并不支持部分填充，也就是说即使是一个双字节也 会缓存其所在行内的所有数据。
The TLBs store the most recently used page-directory and page-table entries. They speed up memory accesses when paging is enabled by reducing the number of memory accesses that are required to read the page tables stored in system memory.
TLB存储了最近使用的页目录和页表项。可以减少读页表时的直接内存访问从而加速分页时的正常内存访问。
MESI(Modified, Exclusive, Shared, Invalid): Cache控制协议用来保持缓存间的一致性。 cache line fill：处理器认为某个从内存的读操作是可缓存时，就会读取整个缓存行到合适的cache上称为缓存行填充。 cache hit： 读取某个内存时发现在cache中存在有效的缓存称为缓存命中。 write hit：对某个可缓存的内存进行写操作会先检查缓存里是否有对应的valid缓存，有的话会先写到缓存上，称为写命中。
内存的缓存类型大概分4种，
MESI是处理器用于保持缓存一致性的协议，L1 data和L2，L3每个缓存行都有自己的状态，这个协议对应用程序是透明的。