File DuplexingPP.v generation

[ariesding0520]

I tried to generated the file DuplexingPP.v by the python scripts. It did generated a file named "DuplexingPP.v". But when I opened the file with a txt viewer, I found that the context in the file is like this: Is this a real verilog file? Is there any thing wrong?

/ Generated by Amaranth Yosys 0.35 (PyPI ver 0.35.0.0.post81, git sha1 cc31c6ebc) /

( \amaranth.hierarchy = "DuplexingPP" ) ( top = 1 ) ( generator = "Amaranth" ) module DuplexingPP(\$2 , \$3 , \$4 , clk, rst, \$1 ); reg \$auto$verilog_backend.cc:2189:dump_module$10 = 0; ( src = "D:\work\prj\trng\lwtrng-main\lwtrng-main\lwtrng\pp\duplexing.py:61" ) input \$1 ; wire \$1 ; ( src = "D:\work\prj\trng\lwtrng-main\lwtrng-main\lwtrng\pp\duplexing.py:85" ) wire [35:0] \$10 ; ( src = "D:\work\prj\trng\lwtrng-main\lwtrng-main\lwtrng\pp\duplexing.py:116" ) wire [199:0] \$100 ; ( src = "D:\work\prj\trng\lwtrng-main\lwtrng-main\lwtrng\pp\duplexing.py:116" ) wire [199:0] \$102 ; ( src = "D:\work\prj\trng\lwtrng-main\lwtrng-main\lwtrng\pp\duplexing.py:116" ) wire [199:0] \$103 ; ( src = "D:\work\prj\trng\lwtrng-main\lwtrng-main\lwtrng\pp\duplexing.py:116" ) wire [199:0] \$105 ; ( src = "D:\work\prj\trng\lwtrng-main\lwtrng-main\lwtrng\pp\duplexing.py:116" ) wire [199:0] \$106 ; ( src = "D:\work\prj\trng\lwtrng-main\lwtrng-main\lwtrng\pp\duplexing.py:116" ) wire [199:0] \$108 ; ( src = "D:\work\prj\trng\lwtrng-main\lwtrng-main\lwtrng\pp\duplexing.py:116" ) wire [199:0] \$109 ; ( src = "D:\work\prj\trng\lwtrng-main\lwtrng-main\lwtrng\pp\duplexing.py:116" ) wire [199:0] \$111 ; ( src = "D:\work\prj\trng\lwtrng-main\lwtrng-main\lwtrng\pp\duplexing.py:116" ) wire [199:0] \$112 ; ( src = "D:\work\prj\trng\lwtrng-main\lwtrng-main\lwtrng\pp\duplexing.py:116" ) wire [199:0] \$114 ; ( src = "D:\work\prj\trng\lwtrng-main\lwtrng-main\lwtrng\pp\duplexing.py:116" ) wire [199:0] \$115 ; reg [1:0] \$117 ; ( src = "D:\work\prj\trng\lwtrng-main\lwtrng-main\lwtrng\pp\duplexing.py:72" )

[kazkojima]

I've updated yosys/amaranth/amaranth-yosys and tried to regenerate .v:

kkojima@wedge:/git/lwtrng/lwtrng/pp/verilog$ rm DuplexingPP.v
kkojima@wedge:/git/lwtrng/lwtrng/pp/verilog$ make
python ../duplexing.py generate -t v > DuplexingPP.v
kkojima@wedge:/git/lwtrng/lwtrng/pp/verilog$ head DuplexingPP.v
/* Generated by Yosys 0.35+39 (git sha1 62bbd086b, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os) */

(* \amaranth.hierarchy  = "DuplexingPP" *)
(* top =  1  *)
(* generator = "Amaranth" *)
module DuplexingPP(z, z_valid, z_ack, clk, rst, sig);
  reg \$auto$verilog_backend.cc:2189:dump_module$3  = 0;
  (* src = "/home/git/lwtrng/lwtrng/pp/verilog/../duplexing.py:85" *)
  wire [35:0] \$1 ;
  (* src = "/home/git/lwtrng/lwtrng/pp/verilog/../duplexing.py:105" *)
kkojima@wedge:/git/lwtrng/lwtrng/pp/verilog$ 

It seems that the verilog comment pairs ( and ) have become (and) in your generated file. It looks the indentations are missing too.

Could you check that with "head"? Some sophisticated text viewers can do this kind of automatic formatting. If the comments are really broken, there may be something wrong with the yosys/amaranth environment.

BTW, my yosys/amaranth versions are

$ pip show amaranth-yosys
Version: 0.35.0.0.post81
$ pip show amaranth
Version: 0.4.dev19+g8b85afa
$ yosys --version
Yosys 0.35+39 (git sha1 62bbd086b, gcc 11.4.0-1ubuntu1~22.04 -fPIC -Os)

[ariesding0520]

Thank you for your response.
I can replace the comment pairs ( and ) with / and /.

I find that in the verilog code you pasted above, the variables are all named as $xxx which is the same as the verilog generated by myself. So why the variables are named in such a way instead of some meaningful strings? It is very hard to understand the code.

[kazkojima]

That verilog code was generated by amaranth/yosys, not by me. One has no control over the names of those machine generated variables. The human readable code is the original python code duplexing.py. It requires knowledge of the amaranth class when reading.

[ariesding0520]

I noticed that you use the keccak-f200 to duplex the raw bits to produce a 32 bit data output. What is the parameter of the keccak-f200 such as the r and c? And also what is the function of the "pad" block? Is the "pad" block only append 192 0s after the 8bits raw data? And also how to select the 2bit from the output of the round function(block "f"), the LSB or the MSB or other bits?

Does the "f" square in the picture refer to keccak's round function[Rnd(A, ir) = ι(χ(π(ρ(θ(A)))), ir)] or the complete keccak-f200 [For ir from 12 + 2l – nr to 12 + 2l – 1, let A = Rnd(A, ir)]? I noticed that a complete keccak-f200 requires exactly 18 round functions to be calculated, which is the same as the number of "f" squares in the picture.

From the picture can I make a conclusion that every 8x18=144 bits raw data produces a 32 bits data output? The input data stream is divided into 144-bit data blocks, and each data block produces a 32-bit output data？

[kazkojima]

Sorry, this is simply my old experiment. It's just code. Hope the code itself answers your questions.