Achievements

[keelimeguy]

The achievements listed are as of commit 2e625863e69b77ada6a6d365be49abee568bcf14.

CPU component

1. Verified simulation of rudimentary input string translator.
2. Verified simulation of streaming element at a given beats-per-minute value.
3. Beginning serial communication support with FPGA.
   • Specifics: A Stimulus (code/src/mymusic/stimulus.sc) is written which passes the string "G3.A3.B3.C4.D4.E4.F#4.(B3D4G4)--." to the system. Tokens within the string represent musical notes[A-Gb#0-9], rests [.], chords[()], and held notes[-]. The string is passed character by character into a Translator (code/src/mymusic/translator.sc), which dynamically constructs a sequence of chord objects from the string of characters. Each note in a chord object is simply represented by a MIDI number. This sequence of chord objects is then passed into a StreamingElement (code/src/mymusic/streaming_element.sc) which transmits these chords at the appropriate frequency, such that they arrive in beat to the symbolized music. A Monitor (code/src/mymusic/monitor.sc) is setup to receive this metronomed chord sequence, and prints each chord with the arrival time. Running the simulation shows each chord beat arrives at intervals 0.375s apart, correctly matching 160 beats-per-minute as specified.

FPGA component

1. Skeleton for FPGA component which can be synthesized and implemented on Nexys 4 DDR.
2. Serial communication capabilities for future interaction with CPU component.
3. Rudimentary control of useful peripherals, including audio output, buttons, switches, and 7-segment display.
   • Specifics: The chosen FPGA is a Nexys 4 DDR, only because I have easy access to one at home. The build structure is organized such that another FPGA with similar peripherals may be used rather easily. A skeleton project was created based on an example GPIO Demo project provided by Digilent. That demo is chosen as it demonstrates UART communication, basic GPIO, and usage of the audio port---providing a good starting place for the needs of this project. That project is modified to allow for receiving of UART messages, as described here. I have synthesized this preliminary project for my Nexys 4 DDR and see that I can communicate with the FPGA through a serial connection (PuTTY). Additionally, I see that the audio port and various GPIO work.

Thus, the basic preliminary requirements for successfully building this project seem to be in place.

[keelimeguy]

Further achievement, as of commit de6820debc91b2b5cf5f94eae467452ec2cdb660.

I have defined a basic encoding for messages sent to the FPGA from the CPU. Messages sent to the FPGA are decoded within "parse_chord()" of the Synthesizer (code/src/mymusic/synthesizer.sc). As there are 128 notes in this implementation, any byte within 0x00-0x7f is associated to that note number. The synthesizer converts the note number into a waveform frequency, so that it can be played as audio later. Additionally, bytes of the form 0xAX will define a volume for the audio, where X is the volume to be set (0x0-0xF). The volume will later determine the amplitude for the synthesized waveform. Finally, a messaged byte of 0x81 and 0x80 will start and stop the audio playback, respectively.

Additionally, an optimization has been made where held notes ..using [-].. do not cause the CPU to re-transmit to the FPGA. This is because the FPGA will continue playing a note until told to stop through the command messaging.

These interactions are modeled in SpecC and print statements are used with timestamps in order to verify the basic functionality.