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keelimeguy / eece7368-project

Final project for EECE 7368, Fall '19
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Next Milestone: Playing Noise from FPGA #2

Closed keelimeguy closed 4 years ago

keelimeguy commented 4 years ago

The next milestone aims to better model the full system with CPU and FPGA components. Then, after simulated verification, implement the methods for playing music from the FPGA.

System

  1. Formalize the protocol that will be used for communicating which notes should be played to the FPGA.
  2. Model in SpecC a complete system interaction with CPU and FPGA, in order to verify FPGA behavior before the VHDL code is written.

FPGA component

  1. Audio waveform generation for allowed musical notes will need researched and implemented.
  2. The concatenation of audio waveforms to create musical chords will need researched and implemented.

Reasoning: The FPGA component should be modeled and verified for functionality in SpecC. This is so that problems with the overall functionality of the waveform synthesis can be determined early and in a much easier language for iterating in. The VHDL code will be written afterwards based on the verified methods from the SpecC code. A basic implementation of waveform generation, e.g. square waves, will be implemented first. Then more refined generation can be added later given time. During this, the communication protocol between CPU and FPGA components will be refined and functionality for controlling the synthesized audio waveform through this protocol will be added and tested.

keelimeguy commented 4 years ago

The milestone is completed, as of commit c9573013d936100d5831f3685ad848a5d9c9f462. Next, support for playing simultaneous notes (chords of size > 1) will be simulated then implemented. Then, work must begin in order to better document and organize the project into the final presentation.