Support VGA timing and support for faster SPI1 bus

[penfold42]

Defaults are unchanged - 15kHZ timing, spi2, dispctl_tristate

Support VGA timing and support for faster SPI1 bus

• config menu for spi bus and pixel clock

Amiga keys

• WASD to move up/down/left/right OSD offsets
• keypad ( ) for VGA/15kHz timing
• keypad + - for sync polarity

Added SAVE+RESET to config menu

• default to this if SPI has changed

Factory default now does a reset

[keirf]

Cheers I should have time to review this next week as I've just got the next rev of Greaseweazle complete and boards at the pcb house 😊

[penfold42]

Sweet

I chose not to squash the SWD and mapr change so they’re super obvious to you

Next on my list

• dispctl config changes - I burnt an hour in final testing cos it’s sort but not quite hard coded

• double line output option. For those who want to use vga/18MHz pixels on SPI2

Thoughts ?

[keirf]

Is the comment in disabling SW JTAG now correct? Looks like you disable full JTAG but keep SWD active?

[keirf]

What do you mean by "dispctl config changes"?

[penfold42]

If SWD is a subset of JTAG your are correct - I enabled SWD.

I want to expose

define DISPCTL_tristate 0 / PB15 is tristate outside OSD; PA15 unused /

define DISPCTL_enable_high 1 / PA15 is Display Enable: Active HIGH /

define DISPCTL_enable_low 2 / PA15 is Display Enable: Active LOW /

uint16_t dispctl_mode;

As config options in the menus - probably as “Output Buffer” none, active height, active low

[keirf]

OK I can fix the comment when I merge.

Re dispctl config and double lines: go for it if you have the time.