Compilation errors after Litex update

[nanortemis]

Hi,

Does not work with the latest Litex

many errors like: /usr/local/lib/python3.7/dist-packages/litex-0.2.dev0-py3.7.egg/litex/soc/software/include/base/irq.h:46:2: error: #error Unsupported architecture ...

[kekiefer]

Confirmed that I see the same issue, but I don't think the fix will be in this repo. It appears that the litex build for vexriscv is now broken because it's missing a definition for __vexriscv__. There were some changes made for picorv32 (enjoy-digital/litex@d149f386c9) that look suspect here, but when reverting litex to just before this I'm having other issues.

picorv32/standard and picorv32/minimal both build, but it still won't boot.

I do see that the Makefile here will have to update litex.soc.tools.mkmscimg -> litex.soc.software.mkmscimg

[kekiefer]

FYI I hacked together this patch to litex that fixed the build for me (in addition to the aforementioned Makefile update):

From e1252a48c609a396b7fcbdc092926fe643d6bb8c Mon Sep 17 00:00:00 2001
From: Kurt Kiefer <kekiefer@gmail.com>
Date: Sat, 27 Apr 2019 14:57:35 -0700
Subject: [PATCH] Hacks to fix vexriscv build

---
 litex/soc/cores/cpu/vexriscv/core.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index f66473be..1effc485 100644
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -49,7 +49,7 @@ class VexRiscv(Module, AutoCSR):
     def __init__(self, platform, cpu_reset_address, variant="standard"):
         assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant

-        self.gcc_flags = GCC_FLAGS[variant]
+        self.gcc_flags = GCC_FLAGS[variant] + " -D__vexriscv__"

         self.platform = platform
         self.variant = variant
@@ -184,7 +184,7 @@ class VexRiscv(Module, AutoCSR):

     @staticmethod
     def add_sources(platform, variant="standard"):
-        cpu_filename = CPU_VARIANTS[variant]
+        cpu_filename = CPU_VARIANTS[variant] + ".v"
         vdir = os.path.join(os.path.abspath(os.path.dirname(__file__)), "verilog")
         platform.add_source(os.path.join(vdir, cpu_filename))

-- 
2.19.2

[nanortemis]

Thanks it worked, the board is booting... I've also built the image using litex-buildenv vexriscv.lite. The build was fine (no modifications), but the board didn't boot :/

[kekiefer]

litex-buildenv is at a version prior to those changes, enjoy-digital/litex@af52842fb

I can't really speak to why litex-buildenv doesn't boot on your board -- I leveraged the machine definition there to build this. Maybe it has something to do with the way the bios image is being created or where it's getting placed in the spi flash?

[enjoy-digital]

@kekiefer thanks, i integrated your fix. Sorry for the troubles. @nanortemis, @kekiefer I'm trying my best to keep things compatible when improving/adding new features, but don't hesitate to ping me if something breaks for you.

[kekiefer]

@enjoy-digital thanks for being so proactive and keeping an eye on things like this -- litex is an awesome project!