[Improvement]: explaining CPU0 and CPU1 relationship

[yf13]

Improvement

Hi,

Thanks a lot for having this repo.

Since I am rather new to Kendryte series of chips, I do have some questions which I can't find answers from docs in this repo:

• What is the relationship between CPU0 and CPU1? as they use different OS so they are quite independent and can be powered on/off independently? Each has its own boot ROM? They are only connected by interrupt signals are shared memory?
• How memory and peripheral devices are assigned to CPU0 and CPU1? How to protect resources assigned to one CPU from being accessed by another CPU1? Who is responsible for initializing the shared resources (e.g. DDR memory controller)?

Regards, yf

[hukaisunny]

1. The operating system of CPU0 is linux, which is mainly responsible for GUI, network and disk; the operating system of CPU1 is RT-SMART, it mainly used for real-time tasks such as multimedia processing and algorithm processing;
2. CPU1 can be powered on and off independently, but when CPU0 is powered off, the entire system will be powered off (including CPU1);
3. Only CPU0 has a bootrom, and CPU1 does not has a bootrom; the software program of CPU1 is loaded by uboot of CPU0;
4. Yes, the communication between CPU0 and CPU1 is through shared memory and interrupts. However, CPU1 is loaded by uboot of CPU0, after loading the program of CPU1 from the disk, CPU0 will set the PC pointer of CPU1, and reset CPU1, CPU1 starts running;
5. The mutual exclusion of CPU0 and CPU1 on the hardware is implemented by two methods; the first method is that only one CPU can access the hardware unit (server CPU), aother CPU (client CPU) will not access directly, instead of send a message to the server CPU. Server CPU will access the hardware unit and return the result to client CPU; the second method is through a hardware mutex, and the two CPUs can mutually exclusive access to the same A hardware resource.

[yf13]

@hukaisunny

Many thanks for the explanations!

can you teach:

• is one openSBI instance there to manage both CPU? or each CPU has its own openSBI instance?
• are there any mechanism to isolate memory region access so that one CPU can't access the other one's private region?

Regards, yf

[hukaisunny]

1. is one openSBI instance there to manage both CPU? or each CPU has its own openSBI instance? each CPU has its own openSBI instance. for CPU0, pmic power on --> hardware reset--->soc init --->bootrom--->uboot--->opensbi--->linux for CPU1, CPU0 uboot( load CPU1 software app to DDR, and set CPU1 pc and unreset CPU1) --> CPU1 opensbi-->CPU1 rt-smart kernel--->CPU1 rt-smart app
2. are there any mechanism to isolate memory region access so that one CPU can't access the other one's private region? yes. for example: CPU0 uboot can load CPU1 software to CPU1 text space, and CPU0 linux cannot access CPU1 text space.

[yf13]

thanks, hope the above explanations can be added to documents later.