I am wondering how to share a memory zone between two CPU cores in SRAM or DDR?
Currently I am using volatile pointers to access the data fields from two cores in M-mode, but still got different data. I am wondering that the independent CPU caches are causing inconsistency.
Can you please teach if there is any way to set that memory zone as non-cacheable for both cores? if not, do you have any suggestions?
Help
I am wondering how to share a memory zone between two CPU cores in SRAM or DDR?
Currently I am using volatile pointers to access the data fields from two cores in M-mode, but still got different data. I am wondering that the independent CPU caches are causing inconsistency.
Can you please teach if there is any way to set that memory zone as non-cacheable for both cores? if not, do you have any suggestions?