It'd be good to add demo code to control specified RISC-V core. Also wondering if there're some levels of details of how two RISC-V cores co-operate and synchronize? Thanks.
Justification
It might arguably true that the behaviour of two RISC-V cores is a mystery. All I can see is the lock example with some sort of interleaving implementation.
Missing feature
It'd be good to add demo code to control specified RISC-V core. Also wondering if there're some levels of details of how two RISC-V cores co-operate and synchronize? Thanks.
Justification
It might arguably true that the behaviour of two RISC-V cores is a mystery. All I can see is the lock example with some sort of interleaving implementation.