Load RAM area in Core1's interrupt context to ensure the cache in Core0 is written back into RAM, instead of use iomen malloc.

[jimaobian]

Code in Core1 like this will ensure the cache in Core0 is written back into RAM.

void core1_interrupt_lock(){
    spinlock_lock(&mMultiInterruptLock);
}

void core1_interrupt_unlock(){
    spinlock_unlock(&mMultiInterruptLock);
}

int test(void *ctx){
    // printk("start\n");
    volatile uint8_t* ptr = lcd_get_color_p();
    if (ptr)
    {
        for (int i = 0; i < 2400; i++)
        {
            *ptr;
            ptr += 64;
        }
    }
    core1_interrupt_unlock();
}