Once issue #9 is implemented it should be trivial to add existing IP blocks to a program.
Initially we should add blocks for:
[x] Blockram
[ ] VGA output
[ ] DSP
Each of the components should be implemented such that the user can simply add a new Blockram(..params..) to the code, and then start using it.
Each component should have a full simulation implementation in SME, and the VHDL generator (possibly also the C++ generator) should recognize the blocks and output a configuration similar to the actual component instead of transpiling the simulator contents.
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Once issue #9 is implemented it should be trivial to add existing IP blocks to a program.
Initially we should add blocks for:
Each of the components should be implemented such that the user can simply add a
new Blockram(..params..)
to the code, and then start using it.Each component should have a full simulation implementation in SME, and the VHDL generator (possibly also the C++ generator) should recognize the blocks and output a configuration similar to the actual component instead of transpiling the simulator contents.