kevinawalsh
commented
1 year ago This seems like a nice idea, but I suspect it would cause trouble for HDL generation. The ram/rom components for HDL generation are fragile enough as it is, and I don't have the vhdl/verilog chops to design true fpga-compatible dual-port memory.
The Dual/Quad options right now are really only designed for the very limited and specific cases of doing properly aligned byte-addressed memory accesses. See the demo/mips circuit for example.
The current RAM features a Dual and Quad port options, but the second port only follows the address +1. Even at that it doesn't work properly, as it will have both ports selecting the same address and cause error half of the time. It would be a lot more useful if the two ports (on Dual mode) were completely independent, having separated addresses as well as read/write pins.