In below case, the parser think "0", "Time", "1", and "Freq" are ports.
I don't know which line make it confuse.
To prevent that I added two "(r'/*', 'block_comment', 'block_comment')," to the parameter/moduel_port description of verilog_tokens.
Then it worked fine.
output reg Store_Type, /*0:Time, 1:Freq*/
always @(negedge rstb, posedge clk)
begin
if (!rstb) begin
Store_Ant <= 0;
Store_Sym <= 0;
Store_Type <= 0; /*0:Time, 1:Freq*/
Store_val <= 0;
end
else begin
...
end
end
In below case, the parser think "0", "Time", "1", and "Freq" are ports. I don't know which line make it confuse.
To prevent that I added two "(r'/*', 'block_comment', 'block_comment')," to the parameter/moduel_port description of verilog_tokens. Then it worked fine.
output reg Store_Type, /*0:Time, 1:Freq*/
always @(negedge rstb, posedge clk) begin if (!rstb) begin Store_Ant <= 0; Store_Sym <= 0; Store_Type <= 0; /*0:Time, 1:Freq*/ Store_val <= 0; end else begin ... end end