verilog parser - parse as a port of a function's port.

[KyleJeong]

I have a module which include a function in a module. In that cases, it thought 'value' and 'lshift' are ports.

module xxx ( aaa );

output reg [1:0] aaa;

function [29:0] lshift45_16; input [44:0] value; input [3:0] lshift; begin case (lshift) 8: lshift45_16 = {value[37: 8]}; 9: lshift45_16 = {value[38: 9]}; 10: lshift45_16 = {value[39:10]}; 11: lshift45_16 = {value[40:11]}; 12: lshift45_16 = {value[41:12]}; 13: lshift45_16 = {value[42:13]}; 14: lshift45_16 = {value[43:14]}; 15: lshift45_16 = {value[44:15]}; default: lshift45_16 = value[44:15]; endcase end endfunction

endmodule