kevinpt / hdlparse

Simple parser for extracting VHDL documentation
http://kevinpt.github.io/hdlparse/
MIT License
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Parsing "output logic" port is wrong #16

Open masics opened 4 years ago

masics commented 4 years ago
output logic [4:1] z, z2

Parsing above gives: Ports: logic output 4 output 1 output z output z2 output