Constants not getting fetched by the parser

[mohit162009]

Hello, For a vhdl file like:

package example is
 CONSTANT MAX_NLBIST              : natural := 128;--changed from 16;
 CONSTANT MAX_NMCUT               : natural := 512;--changed from 96
 CONSTANT MAX_NRAM            : natural := 512;--changed from 96
 CONSTANT MAX_NROM            : natural := 512;--changed from 96

  component demo is
    generic (
      GENERIC1: boolean := false;
      GENERIC2: integer := 100
    );
    port (
      a, b : in std_ulogic := '1';
      c, d : out std_ulogic_vector(7 downto 0);
      e, f : inout unsigned(7 downto 0)
    );
  end component;
end package;

I wrote code to fetch the constants, But I am not getting anything. Could you please help.

import hdlparse.vhdl_parser as vhdl
from hdlparse.vhdl_parser import VhdlConstant
import io

vhdl_ex = vhdl.VhdlExtractor()
vhdl_consts = vhdl_ex.extract_objects('/home/nxf36037/example.vhd', VhdlConstant)

print('Component "{}":'.format(vhdl_consts))

[kevinpt]

I have made the VHDL lexer use case insensitive matching.