kevinpt / hdlparse

Simple parser for extracting VHDL documentation
http://kevinpt.github.io/hdlparse/
MIT License
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Error in parsing the last Output #23

Open Eyantra698Sumanto opened 2 years ago

Eyantra698Sumanto commented 2 years ago

Error in parsing the last Output in a module

module dut(

       input clk,rst,
       output reg [2:0]S1,
       output reg [2:0]S2,
       output reg [2:0]S3,
       output reg [2:0]S4
       );

Parsing the above code gives number of ports for S4 as 1.