Closed Nic30 closed 6 years ago
Hello,
I am working on very similar project https://github.com/Nic30/hdlConvertor . I am using parser/lexer generated from grammar written in ANTLR4 and representing HDL by json like objects.
Are you interested in cooperation?
This parser is intentionally limited to support documentation only. It isn't well suited for fully parsing VHDL or Verilog.
Hello,
I am working on very similar project https://github.com/Nic30/hdlConvertor . I am using parser/lexer generated from grammar written in ANTLR4 and representing HDL by json like objects.
Are you interested in cooperation?