Open Blechzwerg opened 6 years ago
lex.run(text) in parse_verilog(text) failed to correctly interpret portname that contain 'output' or 'input' as part of their name.
I could resolve this by adding word boundaries (\b) to the regexp in 'module' and 'module_port' (here lines 22 and 35, eg.:
'module_port': [ (r'\s*(input|inout|output)\b\s*(reg|supply0|sup... ^^^
regards, b. ;-)
lex.run(text) in parse_verilog(text) failed to correctly interpret portname that contain 'output' or 'input' as part of their name.
I could resolve this by adding word boundaries (\b) to the regexp in 'module' and 'module_port' (here lines 22 and 35, eg.:
regards, b. ;-)