RTL Elaboration failed
INFO: [Common 17-83] Releasing license: Synthesis
205 Infos, 90 Warnings, 0 Critical Warnings and 6 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
while executing
"source [file join $scriptdir "synth.tcl"]"
(file "/home/mint/freedom/fpga-shells/xilinx/common/tcl/vivado.tcl" line 13)
INFO: [Common 17-206] Exiting Vivado at Thu Jun 4 11:32:47 2020...
make: *** [common.mk:81:/home/mint/freedom/builds/vc707-u500devkit/obj/VC707PCIeShell.bit] 错误 1
The BOOTROM_DIR is correct and I can make BOOTROM_DIR=pwd/bootrom/freedom-u540-c000-bootloader -f Makefile.vc707-u500devkit verilog -jnproc successfully. How can I do?
Hi,
When I generate bitstream and bootloader, there is a bug prompting as following.
The command I used is make BOOTROM_DIR=
pwd
/bootrom/freedom-u540-c000-bootloader -f Makefile.vc707-u500devkit mcs -jnproc
ERROR: [Synth 8-439] module 'BootROM' not found [/home/mint/freedom/builds/vc707-u500devkit/sifive.freedom.unleashed.DevKitU500FPGADesign_WithDevKit50MHz.v:323863] ERROR: [Synth 8-6156] failed synthesizing module 'TLMaskROM' [/home/mint/freedom/builds/vc707-u500devkit/sifive.freedom.unleashed.DevKitU500FPGADesign_WithDevKit50MHz.v:323790] ERROR: [Synth 8-6156] failed synthesizing module 'DevKitFPGADesign' [/home/mint/freedom/builds/vc707-u500devkit/sifive.freedom.unleashed.DevKitU500FPGADesign_WithDevKit50MHz.v:430176] ERROR: [Synth 8-6156] failed synthesizing module 'DevKitWrapper' [/home/mint/freedom/builds/vc707-u500devkit/sifive.freedom.unleashed.DevKitU500FPGADesign_WithDevKit50MHz.v:435475] ERROR: [Synth 8-6156] failed synthesizing module 'VC707PCIeShell' [/home/mint/freedom/builds/vc707-u500devkit/sifive.freedom.unleashed.DevKitU500FPGADesign_WithDevKit50MHz.v:435701]
Finished RTL Elaboration : Time (s): cpu = 00:00:47 ; elapsed = 00:00:53 . Memory (MB): peak = 2688.258 ; gain = 721.301 ; free physical = 15914 ; free virtual = 24145
RTL Elaboration failed INFO: [Common 17-83] Releasing license: Synthesis 205 Infos, 90 Warnings, 0 Critical Warnings and 6 Errors encountered. synth_design failed ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
"source [file join $scriptdir "synth.tcl"]" (file "/home/mint/freedom/fpga-shells/xilinx/common/tcl/vivado.tcl" line 13) INFO: [Common 17-206] Exiting Vivado at Thu Jun 4 11:32:47 2020... make: *** [common.mk:81:/home/mint/freedom/builds/vc707-u500devkit/obj/VC707PCIeShell.bit] 错误 1
The BOOTROM_DIR is correct and I can make BOOTROM_DIR=
pwd
/bootrom/freedom-u540-c000-bootloader -f Makefile.vc707-u500devkit verilog -jnproc
successfully. How can I do?Thanks, Jie