Closed kirinyaga closed 12 years ago
I checked MUL & ADD and it does the same thing. It looks like a general problem with EX. For me, EX should overwrite the result, as setting EX should be the last operation done for an instruction, but well, it's up to notch, really. Have someone look at the code that was released by notch for 1.4 ?
I believe devkit is currently in-line with Notch's RC1 emulator. I checked (and fixed) the EX behaviour previously to check this. If it's demonstrable that devkit is wrong, of course I can fix.. I may close this for now though, unless you believe this is the case?
This looks like the code for SHR in notches source long val = (long) a << 16 - b; //Intermediate Value a = (char) (int) (val >> 16); // Whats being set to o = (char) (int) val; //Overflow So if we make whats being set to the same as the o
long val = (long) o << 16 - b; //Intermediate Value o = (char) (int) (val >> 16); // Whats being set to o = (char) (int) val; //Overflow
Plug in the 1's
long val = (long) o << 15; //Intermediate Value o = (char) (int) (val >> 16); // Whats being set to o = (char) (int) val; //Overflow
Simplify o =1 << 14;
Not sure if I made a mistake... check it yourself? Line 224 https://gist.github.com/2403425
You can ignore the line with val >> 16, because it's overwritten with the next line.
o = o << 15
But anyway, that is not the latest emu code from Notch. That's an old version. New version:
this.cycles += 1;
this.ex = (char)(b << '\020' >>> a);
b = (char)(b >> a);
break;
Meaning: this.ex = 1 << 16 >>> 1 and THEN this.ex = 1 >> 16; // i.e. written from B
So EX is overwritten (correctly) with 0.
Going to close this now..
example:
SET EX,1 SHR EX,1
EX should be set to 0x8000 but it is zero. If you do this :
SET A,1 SHR A,1
EX is correctly set to 0x8000.
I don't know how Notch will handle this, but in a real processor, operands are always read before doing the operation, and then written after the operation result is stabilized. There should be zero problem reading and writing to a register, even a state register, at the same time.