kkiningh
commented
4 years ago Unfortunately, this project is unmaintained and I don't think we ever released the final tested version. If you'd like a good systolic design example, please take a look at the gemmini project.
Dear Kevin Kiningham
Hellow. I am Byoungmin Moon in KAIST, Dajeon, Korea.
I have learned deep learing and CNN accelerator and I am studying object detection algorithm and eyeriss, systolic array hardware accelerator.
During studying this, It is too dificult to make verilog code for hardware accelerator, especially contorl logic and PE array and testbench.
Therefore, I searched example code and I found your cs231n project at GitHub.
I learned yout rtl source file. It was good reference to me.
However, i did not understand testbench.
First, I don't know what is simulation target. whether is it top.v or Top.v?
When I saw dc script, you might choose Top and TopTest which contatin only Systolic Array. is it right?
If so, did cocotb play important role to test Systolic design?
I want to know how you test your systolic array. Did you design all of components (mac, systolic array, MatrixInput_sram, AccQueue_sram, etc) and combined them in top, and test it by tb_top.v?
If you did not do that, top.v and tb_top.v is correct code for me to learn?
thank you.
From. Byoung min