Closed rafaelmartins closed 11 months ago
When configuring the active ITM ports to consume, the code uses the same mask for both ITM_TER and ITM_TPR:
ITM_TER
ITM_TPR
https://github.com/klonyyy/STMViewer/blob/4ee85552d1f51cd0c9ba6f5eca58f9c9a4d09d59/src/TraceReader/StlinkTraceDevice.cpp#L66-L67
While it is correct for ITM_TER (each port is a bit in the 32-bit register, max 32 ports), the ITM_TPR register has only 4 bits usable, which represent the ports in groups of 8:
https://developer.arm.com/documentation/ddi0439/b/Instrumentation-Trace-Macrocell-Unit/ITM-programmers-model/ITM-Trace-Privilege-Register--ITM-TPR
This considers Cortex-M4, but the registers work in equivalent way for other variants with ITM.
Hello, thanks for finding it out! I just pushed a fix to the devel branch.
When configuring the active ITM ports to consume, the code uses the same mask for both
ITM_TER
andITM_TPR
:https://github.com/klonyyy/STMViewer/blob/4ee85552d1f51cd0c9ba6f5eca58f9c9a4d09d59/src/TraceReader/StlinkTraceDevice.cpp#L66-L67
While it is correct for
ITM_TER
(each port is a bit in the 32-bit register, max 32 ports), theITM_TPR
register has only 4 bits usable, which represent the ports in groups of 8:https://developer.arm.com/documentation/ddi0439/b/Instrumentation-Trace-Macrocell-Unit/ITM-programmers-model/ITM-Trace-Privilege-Register--ITM-TPR
This considers Cortex-M4, but the registers work in equivalent way for other variants with ITM.