RV32I

[konkitoman]

Implemented from

The RISC-V Instruction Set Manual Volume I Unprivileged Architecture Version 20240411

URET, SRET, MRET extended from https://msyksphinz-self.github.io/riscv-isadoc/html/rvi.html

Instructions

• [x] LUI
• [x] AUIPC
• [x] JAL
• [x] JALR
• [x] BEQ
• [x] BNE
• [x] BLT
• [x] BGE
• [x] BLTU
• [x] BGEU
• [x] LB
• [x] LH
• [x] LW
• [x] LBU
• [x] LHU
• [x] SB
• [x] SH
• [x] SW
• [x] ADDI
• [x] SLTI
• [x] SLTIU
• [x] XORI
• [x] ORI
• [x] ANDI
• [x] SLLI
• [x] SRLI
• [x] SRAI
• [x] ADD
• [x] SUB
• [x] SLL
• [x] SLT
• [x] SLTU
• [x] XOR
• [x] SRL
• [x] SRA
• [x] OR
• [x] AND
• [ ] FENCE as nop
• [ ] FENCE.TSO
• [ ] PAUSE
• [ ] ECALL
• [ ] EBREAK will trow a zig exeption
• [ ] URET
• [ ] SRET
• [ ] MRET