Open kosarev opened 4 years ago
Rather than asserting, could the default implementation behave as though FF is read from the bus to give RST &38? From what I remember from testing IM 0 and IM 1 behave the same if there's nothing providing an instruction on the bus. The timing might be 6T instead of 7T for ack.
Certainly a good idea. 9ae1dad should implement it. Regarding timings: according to my copy of the Sean Young paper, IM 0 and IM 1 both take 13 ticks, which I understand means we have ack(7) write(3) write(3) here.
Now that the assert()
is removed, this looks more like an enhancement rather than a bug.
Aside of #2, this seems to be the only missing feature.