Open kosarev opened 3 years ago
I wasn't aware of the difference in LD A,I / LD A,R behaviour in that case. I'll have to see if I can write a program to detect it, though the always-on RAM contention in the SAM Coupé makes it difficult to do single-cycle adjustments for this particular test.
Perhaps it could be implemented using a new handler that returns whether an interrupt is due in the next N cycles? Those instructions could then check ahead to see if they should change the result in the NMOS case. We need to know exactly when IFF2 is sampled within the instruction though.
I understand we currently implement the CMOS behaviour. For NMOS, yes, we may need to change the way we initiate interrupts by letting the emulator know when ~INT
is going to become active.
We need to know exactly when IFF2 is sampled within the instruction though.
If I remember it correctly that ~INT
is being sampled during the last tick of instruction, then this suggests that we should get its value as it is at that last tick?
https://sinclair.wiki.zxnet.co.uk/wiki/Z80#Differences_between_NMOS_and_CMOS_Z80s says:
From the Q&A clause mentioned:
Related to #27.