Script setting for multiple cores?

[jamesbowman]

When I set LOCAL_MINERS=2, should I expect to see an increased hash rate? I can see that the resource utilization has doubled, but the speed remains 2.33kH/s:

new target 00000492 diff 56
06f0aafb416d8e9e0aa8595a788ff8e91384ebe2135839f57367383302000000
c9126b44155767a6345f2a8e2dd9c8aef91396a71c77a80fa8f3597b2026921c
00000000000000000000000080000000000000005bd7101b525ed3526fd8e104
target 00000492
[01/12/2014 19:33:08] 2.33 kH/s (~0.00 kH/s) [Rej: 0/0 (0.00%)] n=0006f64e
[01/12/2014 19:33:10] 2.33 kH/s (~0.00 kH/s) [Rej: 0/0 (0.00%)] n=00070879
[01/12/2014 19:33:12] 2.33 kH/s (~0.00 kH/s) [Rej: 0/0 (0.00%)] n=00071aa3
[01/12/2014 19:33:14] 2.33 kH/s (~0.00 kH/s) [Rej: 0/0 (0.00%)] n=00072cce
[01/12/2014 19:33:16] 2.33 kH/s (~0.00 kH/s) [Rej: 0/0 (0.00%)] n=00073ef7
[01/12/2014 19:33:18] 2.33 kH/s (~0.00 kH/s) [Rej: 0/0 (0.00%)] n=00075122

is there something in the scripts side to enable multiple cores?

[kramble]

It depends on the FPGA. You haven't said which one you're using (but its the TCL miner so I assume its an Altera). LOCAL_MINERS=2 won't work on the DE0-Nano (EP4CE22), so it must be another device which I won't have benchmarked. However for the LX150 (different family, I know), the dual core only performs marginally faster than the single core (the reasons are complicated, involving TMTO with fixed RAM size, and reduced FMAX due to higher utilization).

Also the 2.33 kH/s seems rather slow, (I don't recall whether this is accurate or not, but I think I fixed the mining script), so it must be a smaller device. Anyway enough speculation, TELL ME WHAT YOU ARE DOING (please).

[jamesbowman]

The FPGA is an Altera Stratix III, EP3SL150F1152C2.

I'm running the DE0-Nano build. To build it, I removed the PLL module and hooked up the 50 MHz board clock as input.

[kramble]

OK, a quick google gives me 142kLE and 5499kBit RAM for the EP3SP150, so that should perform at least as well as a LX150, probably a bit faster, so you could expect 15 to 20kHash/sec.

Rather than starting from the DE0-Nano build which is for a much smaller device, I suggest using the DE2-115 build as a base, ( https://github.com/kramble/FPGA-Litecoin-Miner/tree/master/experimental/DE2-115-SLOWSIXTEEN ) as it should fit the device better.

It hasn't actually been tested by me (I don't have the board, and the person I did it for is actually running on a SoCKit device rather than the EP4CE115), but it should work OK.

I don't recommend removing the PLL as you lose the ability to vary the clock speed, and while 50MHz should be fine for a single core, it may be a bit tight for the dual core. If the original PLL won't compile for a Stratix, just use the wizard to re-create it.

Note that the design may not meet timing closure at these speeds but overclocking is pretty much the norm for crypto-currency mining so the tendency is just to clock it as fast as the device will go without an excessive error rate. (Usually setting the clock speed at runtime, for which the PLL is very useful, though I've only implemented this in the Xilinx port as the Altera PLL is more awkward to program). So just start off slow (25MHz should be OK for a single core), and once that is working, ramp it up. The dual core build is worth trying, but don't expect double the performance, in practice on the LX150 it was barely any faster than the single core build (there are good reasons to expect this due to the doubled TMTO/LOOKUP_GAP and a slower clock for the higher utilization).

Have fun!