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kunalg123 / vsdflow

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.
Apache License 2.0
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STA failing #3

Closed dsnaveen1 closed 3 years ago

dsnaveen1 commented 4 years ago

after running post STA failing without any log file creation

kunalg123 commented 4 years ago

Really apologize for such a huge delay in responding. Mostly, other are reporting issues over my udemy channel, so didn't had a chance to check this

I have to fix this, till then here's the workaround: From vsdflow directory, do the below: unzip OpenSTA-master.zip cd OpenSTA-master mkdir build cd build cmake .. make cd .. sudo rm -rf /usr/bin/sta sudo ln -s $PWD/app/sta /usr/bin/sta

Now try running vsdflow again and see if it works

dsnaveen1 commented 4 years ago

Thanks Kunal,

It is working now