VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.
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The vsdflow in the example stuck at last line "Info: Initializing number of threads, libraries, sdc, verilog netlist path... " Directory not getting created #4
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An unique User Interface (UI) that will take RTL netlist & SDC constraints as an input, and will generate
sythnesized netlist & pre-layout timing report as an output. It uses Yosys open-source tool for synthesis
and Opentimer to generate pre-layout timing reports.
Developed and Maintained by VLSI System Design Corporation Pvt. Ltd.
For any queries and bugs, please drop a mail to kunalpghosh@gmail.com
********* A vlsisystemdesign.com initiative *********
-------------- Below settings will ensure the correct behavior of vsdsynth -------------------
-----Please review below settings with VSD team or drop an email to kunalpghosh@gmail.com-----
Set your technology using variable "tech_name"
Setting technology to osu018
This is the place where all procs are located
Setting variable 'proc_dir' to procs
tcl_precision specifies the number of digits to generate when converting floating point values to strings
Setting variable 'tcl_precision' to 3
Set runsynthesis variable to '1' if you want to run synthesis. If you want to use the.prelayout.timing.rpt of previous runs. which is stored in outdir, set this variable to '0' to skip synthesis and jump to STA
Setting variable 'run_synthesis' to 1
Set generatesdc to '1' if you want to generate SDC from data given in excel sheet. If you already have sdc, save it in outdir as .sdc and set this variable to '0'
Setting variable 'generate_sdc' to 1
Set enable_prelayout_timing to '1' for running STA with zero-wire load parasitics. If you have generated spef, set this variable to '0'
Setting variable 'enable_prelayout_timing' to 1
Set do_STA to '1' if you want to run STA after synthesis. Else, set this variable to '0'
Setting variable 'do_STA' to 1
Set generate_report to '1' if you want to generate QOR of your design. Else, set this variable to '0'
Setting variable 'generate_report' to 0
If generate_report is '1', there are currently 2 kinds of reporting format we provide. If you need horizontal reporting, set generate_horizontal_report to '1'
Setting variable 'generate_horizontal_report' to 1
If generate_report is '1', there are currently 2 kinds of reporting format we provide. If you need vertical reporting, set generate_horizontal_report to '1'
Setting variable 'generate_vertical_report' to 1
If run_place_and_route is '1', it will run placement and routing
Setting variable 'run_place_and_route' to 1
Info: Setting Design Name as 'spi_slave'
Info: Setting Output Directory as 'outdir_spi_slave'
Info: Setting Netlist Directory as 'verilog'
Info: Setting Early Library Path as '/usr/local/share/qflow/tech/osu018/osu018_stdcells.lib'
Info: Setting Late Library Path as '/usr/local/share/qflow/tech/osu018/osu018_stdcells.lib'
Info: Setting Constraints File as 'spi_slave_design_constraints.csv'
Info: Below are the list of initial variables and their values. User can use these variables for further debug. Use 'puts ' command to query value of below variables
DesignName = spi_slave
OutputDirectory = /home/rakesh/vsd/vsdflow/outdir_spi_slave
NetlistDirectory = /home/rakesh/vsd/vsdflow/verilog
EarlyLibraryPath = /usr/local/share/qflow/tech/osu018/osu018_stdcells.lib
LateLibraryPath = /usr/local/share/qflow/tech/osu018/osu018_stdcells.lib
ConstraintsFile = /home/rakesh/vsd/vsdflow/spi_slave_design_constraints.csv
Info: Early cell library found in path /usr/local/share/qflow/tech/osu018/osu018_stdcells.lib
Info: Late cell library found in path /usr/local/share/qflow/tech/osu018/osu018_stdcells.lib
Info: Output directory found in path /home/rakesh/vsd/vsdflow/outdir_spi_slave
Info: RTL netlist directory found in path /home/rakesh/vsd/vsdflow/verilog
Info: Constraints file found in path /home/rakesh/vsd/vsdflow/spi_slave_design_constraints.csv
Info: Dumping SDC constraints for spi_slave
Info-SDC: Working on clock constraints.....
Info-SDC: Working on IO constraints.....
Info-SDC: Categorizing input ports as bits and bussed
Info-SDC: Working on IO constraints.....
Info-SDC: Categorizing output ports as bits and bussed
Info: SDC created. Please use constraints in path /home/rakesh/vsd/vsdflow/outdir_spi_slave/spi_slave.sdc
Starting synthesis using qflow
Synthesis finished without errors
Please review log file "/home/rakesh/vsd/vsdflow/outdir_spi_slave/log/synth.log" for errors/warnings
Info: Please find the synthesized netlist for spi_slave at below path. You can use this netlist for STA or PNR
Info: Initializing number of threads, libraries, sdc, verilog netlist path...
Info: enable_prelayout_timing is 1. Enabling zero-wire load parasitics
Info: Timing Analysis Started....
Info: Initializing number of threads, libraries, sdc, verilog netlist path...
input conf file is /home/rakesh/vsd/vsdflow/outdir_spi_slave/spi_slave.prelayout.conf
output report file is /home/rakesh/vsd/vsdflow/outdir_spi_slave/spi_slave.prelayout.timing.rpt
Info: STA finished in 0sec seconds
Info: Refer to /home/rakesh/vsd/vsdflow/outdir_spi_slave/spi_slave.prelayout.timing.rpt for warnings and errors
Info: Pre-layout STA finished
Creating a backup of synthesis netlist
Place and Route step from qflow started
Place and Route step from qflow finished
Info: Post-layout STA started
Info: Timing Analysis Started....
Info: Initializing number of threads, libraries, sdc, verilog netlist path...
Kill the above run
From vsdflow directory, do the below
unzip OpenSTA-master.zip
cd OpenSTA-master
mkdir build
cd build
cmake ..
make
cd ..
sudo rm -rf /usr/bin/sta
sudo ln -s $PWD/app/sta /usr/bin/sta
kunalg123
commented
4 years ago
-------------- Below settings will ensure the correct behavior of vsdsynth ------------------- -----Please review below settings with VSD team or drop an email to kunalpghosh@gmail.com-----
Set your technology using variable "tech_name" Setting technology to osu018 This is the place where all procs are located Setting variable 'proc_dir' to procs
tcl_precision specifies the number of digits to generate when converting floating point values to strings Setting variable 'tcl_precision' to 3
Set runsynthesis variable to '1' if you want to run synthesis. If you want to use the.prelayout.timing.rpt of previous runs. which is stored in outdir, set this variable to '0' to skip synthesis and jump to STA
Setting variable 'run_synthesis' to 1
Set generatesdc to '1' if you want to generate SDC from data given in excel sheet. If you already have sdc, save it in outdir as .sdc and set this variable to '0'
Setting variable 'generate_sdc' to 1
Set enable_prelayout_timing to '1' for running STA with zero-wire load parasitics. If you have generated spef, set this variable to '0' Setting variable 'enable_prelayout_timing' to 1
Set do_STA to '1' if you want to run STA after synthesis. Else, set this variable to '0' Setting variable 'do_STA' to 1
Set generate_report to '1' if you want to generate QOR of your design. Else, set this variable to '0' Setting variable 'generate_report' to 0
If generate_report is '1', there are currently 2 kinds of reporting format we provide. If you need horizontal reporting, set generate_horizontal_report to '1' Setting variable 'generate_horizontal_report' to 1
If generate_report is '1', there are currently 2 kinds of reporting format we provide. If you need vertical reporting, set generate_horizontal_report to '1' Setting variable 'generate_vertical_report' to 1
If run_place_and_route is '1', it will run placement and routing Setting variable 'run_place_and_route' to 1
Info: Setting Design Name as 'spi_slave'
Info: Setting Output Directory as 'outdir_spi_slave'
Info: Setting Netlist Directory as 'verilog'
Info: Setting Early Library Path as '/usr/local/share/qflow/tech/osu018/osu018_stdcells.lib'
Info: Setting Late Library Path as '/usr/local/share/qflow/tech/osu018/osu018_stdcells.lib'
Info: Setting Constraints File as 'spi_slave_design_constraints.csv'
Info: Below are the list of initial variables and their values. User can use these variables for further debug. Use 'puts' command to query value of below variables
DesignName = spi_slave
OutputDirectory = /home/rakesh/vsd/vsdflow/outdir_spi_slave
NetlistDirectory = /home/rakesh/vsd/vsdflow/verilog
EarlyLibraryPath = /usr/local/share/qflow/tech/osu018/osu018_stdcells.lib
LateLibraryPath = /usr/local/share/qflow/tech/osu018/osu018_stdcells.lib
ConstraintsFile = /home/rakesh/vsd/vsdflow/spi_slave_design_constraints.csv
Info: Early cell library found in path /usr/local/share/qflow/tech/osu018/osu018_stdcells.lib
Info: Late cell library found in path /usr/local/share/qflow/tech/osu018/osu018_stdcells.lib
Info: Output directory found in path /home/rakesh/vsd/vsdflow/outdir_spi_slave
Info: RTL netlist directory found in path /home/rakesh/vsd/vsdflow/verilog
Info: Constraints file found in path /home/rakesh/vsd/vsdflow/spi_slave_design_constraints.csv
Info: Dumping SDC constraints for spi_slave
Info-SDC: Working on clock constraints.....
Info-SDC: Working on IO constraints.....
Info-SDC: Categorizing input ports as bits and bussed
Info-SDC: Working on IO constraints.....
Info-SDC: Categorizing output ports as bits and bussed
Info: SDC created. Please use constraints in path /home/rakesh/vsd/vsdflow/outdir_spi_slave/spi_slave.sdc
Starting synthesis using qflow
Synthesis finished without errors
Please review log file "/home/rakesh/vsd/vsdflow/outdir_spi_slave/log/synth.log" for errors/warnings
Info: Please find the synthesized netlist for spi_slave at below path. You can use this netlist for STA or PNR
/home/rakesh/vsd/vsdflow/outdir_spi_slave/synthesis/spi_slave_synth.rtlbb.v
Info: Pre-layout STA started
Info: Timing Analysis Started....
Info: Initializing number of threads, libraries, sdc, verilog netlist path...
Info: enable_prelayout_timing is 1. Enabling zero-wire load parasitics
Info: Timing Analysis Started....
Info: Initializing number of threads, libraries, sdc, verilog netlist path... input conf file is /home/rakesh/vsd/vsdflow/outdir_spi_slave/spi_slave.prelayout.conf output report file is /home/rakesh/vsd/vsdflow/outdir_spi_slave/spi_slave.prelayout.timing.rpt
Info: STA finished in 0sec seconds
Info: Refer to /home/rakesh/vsd/vsdflow/outdir_spi_slave/spi_slave.prelayout.timing.rpt for warnings and errors
Info: Pre-layout STA finished
Creating a backup of synthesis netlist
Place and Route step from qflow started
Place and Route step from qflow finished
Info: Post-layout STA started
Info: Timing Analysis Started....
Info: Initializing number of threads, libraries, sdc, verilog netlist path...