kunalg123 / vsdflow

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.
Apache License 2.0
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unable to fix error in lvs #6

Open dsnaveen1 opened 3 years ago

dsnaveen1 commented 3 years ago

Run parallel Netgen with 'mpirun -np xy netgen' optfile ./ng.opt does not exist - using default values togl-version : 2 OCC module loaded ERROR: This operation needs a mesh errinfo: This operation needs a mesh while executing "Ng_ExportMesh $file $exportfiletype" invoked from within ".#ngmenu.#ngmenu#file invoke active" ("uplevel" body line 1) invoked from within "uplevel #0 [list $w invoke active]" (procedure "tk::MenuInvoke" line 50) invoked from within "tk::MenuInvoke .#ngmenu.#ngmenu#file 1" (command bound to event) Thank you for using NETGEN netgen failure: No file comp.out. Premature exit. Synthesis flow stopped due to error condition.