Support recent binutils

[jserv]

From version 2.38, binutils default to ISA spec version 20191213. This means that the csr read/write (csrr/csrw) instructions and fence.i instruction has separated from the I extension, become two standalone extensions: Zicsr and Zifencei. As the kernel uses those instruction, this causes the following build failure:

riscv-none-elf-gcc -march=rv32im -mabi=ilp32   -c -o startup.o startup.S
startup.S: Assembler messages:
startup.S:5: Error: unrecognized opcode `csrw mtvec,t0'
startup.S:6: Error: unrecognized opcode `csrrsi zero,mtvec,1'
startup.S:74: Error: unrecognized opcode `csrr t5,mepc'
startup.S:76: Error: unrecognized opcode `csrw mepc,t5'
startup.S:133: Error: unrecognized opcode `csrr t5,mepc'
startup.S:135: Error: unrecognized opcode `csrw mepc,t5'
startup.S:192: Error: unrecognized opcode `csrr t5,mepc'
startup.S:194: Error: unrecognized opcode `csrw mepc,t5'

With #9, recent GNU toolchains which support binutils 2.38+ can reproduce the above issue. Then, I attempted to apply the follow change:

--- a/sw/common/Makefile.common
+++ b/sw/common/Makefile.common
@@ -14,7 +14,7 @@ READELF := $(CROSS_COMPILER)readelf
 ifeq ($(rv32c), 1)
 ARCH    := -march=rv32imac -mabi=ilp32
 else
-ARCH    := -march=rv32im -mabi=ilp32
+ARCH    := -march=rv32im_zicsr -mabi=ilp32
 endif

 CFLAGS  := -O3 -Wall $(ARCH) -nostartfiles -nostdlib

make all can therefore generate RISC-V ELF files. However, the ISA simulator failed to load the coremark

clang++    getch.o sim_main.o verilated.o verilated_dpi.o verilated_fst_c.o Vriscv__ALL.a   -lz    -o sim
Illegal instruction at PC 0x000087fc
Illegal instruction at PC 0x00008808
Illegal instruction at PC 0x00008810
Illegal instruction at PC 0x00008814
Illegal instruction at PC 0x00008818
...

If compilation flag is set to -march=rv32im, coremark.elf is still built.

Reference: [PATCH] riscv: Fix build against binutils 2.38

[kuopinghsu]

This would be an issue. The xPack GNU RISC-V Embedded GCC doesn't provide rv32im_zicsr library. Since there is no rv32im_zicsr multilib in the library folder, the compiler will link the default library (You can use the "-Wl,--verbose" linking option to see how the compiler resolves the library link order). The default libc.a is compiled with the RV32C instruction set, which can be problematic when using the standard C library. So when you run coremark with the rv32im_zicsr -march option, it gets an illegal compressed instructions in the memset function.

The temporary solution is using "--with-isa-spec=2.2" to use older ISA spec. It does not reflect the latest RISC-V standard and will likely become unmaintainable in the near future. The best solution is xPack GNU RISC-V Embedded GCC which provides rv32im_zicsr lirary.

[jserv]

The temporary solution is using "--with-isa-spec=2.2" to use older ISA spec. It does not reflect the latest RISC-V standard and will likely become unmaintainable in the near future. The best solution is xPack GNU RISC-V Embedded GCC which provides rv32im_zicsr lirary.

Thus, please report to riscv-none-elf-gcc-xpack with the concern of rv32im_zicsr built library.

[kuopinghsu]

The xPack GNU RISC-V Embedded GCC is only a binary distribution of the SiFive RISC-V GNU Embedded Toolchain, and does not intend to add new functionality, or to fix existing problems. This is toolchain issues. I have updated Building Toolchains section to build up defaul ISA spec to 20191213, you can build the toolchains from the source.