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kuznia-rdzeni / coreblocks

RISC-V out-of-order core for education and research purposes
https://kuznia-rdzeni.github.io/coreblocks/
BSD 3-Clause "New" or "Revised" License
37 stars 15 forks source link

Make the processor superscalar #261

Open tilk opened 1 year ago

tilk commented 1 year ago

This issue involves extending the processor so that it can process more than one instruction per cycle. As functional units should naturally scale, the main problem is extending the frontend (to load multiple instructions at once) and backend (to commit multiple instructions at once).

lekcyjna123 commented 1 year ago

It can be useful to check what is/was implemented in vector extension, because there are similar problems as with superscalarity