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kuznia-rdzeni / coreblocks

RISC-V out-of-order core for education and research purposes
https://kuznia-rdzeni.github.io/coreblocks/
BSD 3-Clause "New" or "Revised" License
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Implement Zicond #628

Open tilk opened 7 months ago

tilk commented 7 months ago

The Zicond extension extends the architecture with conditional instructions, which allow to create code with less branches. It's probably the best to implement this in ALU.

Hazardu commented 2 weeks ago

When trying to implement Zicond, I came across enums of different shapes named Funct3 and Funct7 in isa_consts.py but I can't find any descriptions what they are supposted to describe exactly and what their values mean.

I see that they are used when defining the encodings of operation types in instr_description.py

Encoding(Opcode.OP, Funct3.ADD, Funct7.ADD),

as well as used differently in alu.py to describe instructions

(self.Fn.ADD, OpType.ARITHMETIC, Funct3.ADD, Funct7.ADD),

but I dont understand what their values represent (like previousely mentioned Funct3.ADD and Funct7.ADD equal 0) Could you please explain?

piotro888 commented 2 weeks ago

image @Hazardu Opcode/Funct* are fields from raw RISC-V instruction encoding.

Optype is our internal representation of instruction groups (as replacement of Opcode), used also as an only factor for routing instructions to Functional Units. Optype is resolved in Decode stage.

Functional units have their own small internal decoders that convert Optype (from instruction_description.py) and Funct3, Funct7 (from raw instruction; Funct7 is not always present or needed [if Optype+Funct3 are unique]) to specific unique FU operation (to self.Fn)

Zicond should have separate Optype as it is separate extension.