kuznia-rdzeni / coreblocks

RISC-V out-of-order core for education and research purposes
https://kuznia-rdzeni.github.io/coreblocks/
BSD 3-Clause "New" or "Revised" License
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Add a trap handler to benchmarks #658

Closed xThaid closed 2 months ago

xThaid commented 5 months ago

Right now if an exception is raised during the execution of benchmarks, the core will jump to 0x0 (the default value of mtvec) and will keep executing the code. This will result in a benchmark timeout - cryptic failure, hard to debug, long execution time. Instead, we could add a trap handler to crt0.S of benchmarks, so in the case of an exception the handler could write all useful information to the MMIO and terminate the simulation right away.