search

kuznia-rdzeni / coreblocks

RISC-V out-of-order core for education and research purposes
https://kuznia-rdzeni.github.io/coreblocks/
BSD 3-Clause "New" or "Revised" License
36 stars 14 forks source link

Sort benchmarks #671

Closed tilk closed 5 months ago

tilk commented 5 months ago

The changing order of benchmarks in the metrics table is driving me crazy. This PR fixes that.

github-actions[bot] commented 5 months ago

Benchmarks summary

Performance benchmarks

aha-mont64 crc32 minver nettle-sha256 nsichneu slre statemate ud
0.404 (0.000) 0.457 (0.000) 0.311 (0.000) 0.643 (0.000) 0.345 (0.000) 0.256 (0.000) 0.304 (0.000) 0.398 (0.000)

You can view all the metrics here.

Synthesis benchmarks (basic)

Device utilisation: (ECP5) LUTs used as DFF: (ECP5) LUTs used as carry: (ECP5) LUTs used as ram: (ECP5) Max clock frequency (Fmax)
🔻 21829 (-772) 5560 (0) 🔻 770 (-32) 1004 (0) 🔺 53 (+4)

Synthesis benchmarks (full)

Device utilisation: (ECP5) LUTs used as DFF: (ECP5) LUTs used as carry: (ECP5) LUTs used as ram: (ECP5) Max clock frequency (Fmax)
🔻 32896 (-755) 8802 (0) 1938 (0) 1184 (0) 🔻 42 (-1)
github-actions[bot] commented 5 months ago

Benchmarks summary

Performance benchmarks

aha-mont64 crc32 minver nettle-sha256 nsichneu slre statemate ud
0.406 (0.000) 0.457 (0.000) 0.308 (0.000) 0.644 (0.000) 0.345 (0.000) 0.255 (0.000) 0.304 (0.000) 0.398 (0.000)

You can view all the metrics here.

Synthesis benchmarks (basic)

Device utilisation: (ECP5) LUTs used as DFF: (ECP5) LUTs used as carry: (ECP5) LUTs used as ram: (ECP5) Max clock frequency (Fmax)
🔻 22376 (-1217) 5560 (0) 🔺 802 (+32) 1004 (0) 🔺 50 (+3)

Synthesis benchmarks (full)

Device utilisation: (ECP5) LUTs used as DFF: (ECP5) LUTs used as carry: (ECP5) LUTs used as ram: (ECP5) Max clock frequency (Fmax)
🔻 29357 (-3284) 8802 (0) 1970 (0) 1184 (0) 🔻 42 (-4)