Measure trap latency

[tilk]

This PR adds yet another metric, this time we're measuring the amount of cycles the core flushes itself after a trap.

After looking at the metrics, I have the following conclusion:

• A significant number of cycles is spent in flushing - in the slre benchmark it's more than half!

[github-actions[bot]]

Benchmarks summary

Performance benchmarks

aha-mont64	crc32	minver	nettle-sha256	nsichneu	slre	statemate	ud
0.404 (0.000)	0.457 (0.000)	0.311 (0.000)	0.643 (0.000)	0.345 (0.000)	0.256 (0.000)	0.304 (0.000)	0.398 (0.000)

You can view all the metrics here.

Synthesis benchmarks (basic)

Device utilisation: (ECP5)	LUTs used as DFF: (ECP5)	LUTs used as carry: (ECP5)	LUTs used as ram: (ECP5)	Max clock frequency (Fmax)
🔻 21730 (-871)	5560 (0)	🔻 770 (-32)	1004 (0)	🔺 49 (+1)

Synthesis benchmarks (full)

Device utilisation: (ECP5)	LUTs used as DFF: (ECP5)	LUTs used as carry: (ECP5)	LUTs used as ram: (ECP5)	Max clock frequency (Fmax)
🔻 31378 (-2273)	8802 (0)	🔺 1970 (+32)	1184 (0)	🔺 43 (+1)

[github-actions[bot]]

Benchmarks summary

Performance benchmarks

aha-mont64	crc32	minver	nettle-sha256	nsichneu	slre	statemate	ud
0.407 (0.000)	0.527 (0.000)	0.321 (0.000)	0.652 (0.000)	0.345 (0.000)	0.283 (0.000)	0.317 (0.000)	0.405 (0.000)

You can view all the metrics here.

Synthesis benchmarks (basic)

Device utilisation: (ECP5)	LUTs used as DFF: (ECP5)	LUTs used as carry: (ECP5)	LUTs used as ram: (ECP5)	Max clock frequency (Fmax)
🔻 22063 (-39)	5560 (0)	🔺 802 (+32)	1004 (0)	🔻 49 (-2)

Synthesis benchmarks (full)

Device utilisation: (ECP5)	LUTs used as DFF: (ECP5)	LUTs used as carry: (ECP5)	LUTs used as ram: (ECP5)	Max clock frequency (Fmax)
🔻 32504 (-1251)	8802 (0)	🔺 1970 (+32)	1184 (0)	🔺 43 (+1)