kuznia-rdzeni / coreblocks

RISC-V out-of-order core for education and research purposes
https://kuznia-rdzeni.github.io/coreblocks/
BSD 3-Clause "New" or "Revised" License
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Stall fetch on JALR instruction #674

Closed xThaid closed 2 months ago

xThaid commented 2 months ago

If we don't have a prediction for the target of a JALR instruction (so always now), the best we can do is to stall the fetch unit.

github-actions[bot] commented 2 months ago

Benchmarks summary

Performance benchmarks

aha-mont64 crc32 minver nettle-sha256 nsichneu slre statemate ud
🔺 0.405 (+0.001) 🔺 0.527 (+0.070) 🔺 0.320 (+0.009) 🔺 0.651 (+0.008) 🔺 0.345 (+0.001) 🔺 0.284 (+0.028) 🔺 0.318 (+0.014) 🔺 0.406 (+0.007)

You can view all the metrics here.

Synthesis benchmarks (basic)

Device utilisation: (ECP5) LUTs used as DFF: (ECP5) LUTs used as carry: (ECP5) LUTs used as ram: (ECP5) Max clock frequency (Fmax)
🔻 22524 (-77) 5560 (0) 802 (0) 1004 (0) 🔺 51 (+2)

Synthesis benchmarks (full)

Device utilisation: (ECP5) LUTs used as DFF: (ECP5) LUTs used as carry: (ECP5) LUTs used as ram: (ECP5) Max clock frequency (Fmax)
🔺 34744 (+1093) 8802 (0) 1938 (0) 1184 (0) 🔻 40 (-2)
github-actions[bot] commented 2 months ago

Benchmarks summary

Performance benchmarks

aha-mont64 crc32 minver nettle-sha256 nsichneu slre statemate ud
🔺 0.407 (+0.001) 🔺 0.527 (+0.070) 🔺 0.321 (+0.013) 🔺 0.652 (+0.008) 🔺 0.345 (+0.001) 🔺 0.283 (+0.028) 🔺 0.317 (+0.014) 🔺 0.405 (+0.007)

You can view all the metrics here.

Synthesis benchmarks (basic)

Device utilisation: (ECP5) LUTs used as DFF: (ECP5) LUTs used as carry: (ECP5) LUTs used as ram: (ECP5) Max clock frequency (Fmax)
🔺 25021 (+1223) 5560 (0) 802 (0) 1004 (0) 🔻 47 (-4)

Synthesis benchmarks (full)

Device utilisation: (ECP5) LUTs used as DFF: (ECP5) LUTs used as carry: (ECP5) LUTs used as ram: (ECP5) Max clock frequency (Fmax)
🔻 30062 (-2338) 8802 (0) 🔺 1970 (+32) 1184 (0) 🔺 43 (+6)