search

kuznia-rdzeni / coreblocks

RISC-V out-of-order core for education and research purposes
https://kuznia-rdzeni.github.io/coreblocks/
BSD 3-Clause "New" or "Revised" License
33 stars 13 forks source link

[don't merge] workflow test #676

Closed xThaid closed 2 months ago

github-actions[bot] commented 2 months ago

Benchmarks summary

Performance benchmarks

aha-mont64 crc32 minver nettle-sha256 nsichneu slre statemate ud
▼ 0.402 (-0.005) ▼ 0.527 (-0.000) ▼ 0.319 (-0.002) ▲ 0.652 (+0.001) ▼ 0.319 (-0.026) ▲ 0.284 (+0.001) ▼ 0.317 (-0.000) ▼ 0.405 (-0.000)

You can view all the metrics here.

Synthesis benchmarks (basic)

Device utilisation: (ECP5) LUTs used as DFF: (ECP5) LUTs used as carry: (ECP5) LUTs used as ram: (ECP5) Max clock frequency (Fmax)
▼ 21528 (-2669) 5560 (0) ▲ 802 (+32) 1004 (0) ▲ 49 (+4)

Synthesis benchmarks (full)

Device utilisation: (ECP5) LUTs used as DFF: (ECP5) LUTs used as carry: (ECP5) LUTs used as ram: (ECP5) Max clock frequency (Fmax)
▼ 27804 (-5785) ▼ 8014 (-788) ▼ 1644 (-294) 1184 (0) ▼ 42 (-1)