Components at top level in Transactron

[tilk]

This PR allows to create a top-level Transactron component, which can be easily used in synthesis. Changes:

• TransactionComponent was added, which performs the same role as TransactionModule, but for Components. Internal interface is forwarded to the top level.
• Transactron Adapters are now components.
• Verilog generation was changed to take advantage of signatures of components, if present.
• Synthesis benchmark script was changed so that interfaces of components are automatically mapped to pins.

Benchmarks run to make sure synthesis still works in CI.

Fixes #706.

TODO:

• [x] Simplify synthesize.py too.

[github-actions[bot]]

Benchmarks summary

Performance benchmarks

aha-mont64	crc32	minver	nettle-sha256	nsichneu	slre	statemate	ud
0.426 (0.000)	0.513 (0.000)	0.351 (0.000)	0.655 (0.000)	0.364 (0.000)	0.293 (0.000)	0.329 (0.000)	0.435 (0.000)

You can view all the metrics here.

Synthesis benchmarks (basic)

Device utilisation: (ECP5)	LUTs used as DFF: (ECP5)	LUTs used as carry: (ECP5)	LUTs used as ram: (ECP5)	Max clock frequency (Fmax)
▼ 21972 (-372)	5762 (0)	802 (0)	▼ 892 (-4)	▼ 47 (-2)

Synthesis benchmarks (full)

Device utilisation: (ECP5)	LUTs used as DFF: (ECP5)	LUTs used as carry: (ECP5)	LUTs used as ram: (ECP5)	Max clock frequency (Fmax)
▼ 30235 (-4003)	9015 (0)	1976 (0)	▼ 1072 (-4)	▲ 41 (+2)