kuznia-rdzeni / coreblocks

RISC-V out-of-order core for education and research purposes
https://kuznia-rdzeni.github.io/coreblocks/
BSD 3-Clause "New" or "Revised" License
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Add support for target prediction in JumpBranch unit #711

Closed xThaid closed 1 month ago

xThaid commented 1 month ago

This PR prepares the jump branch unit for JALR target prediction. To do so I did the following changes:

github-actions[bot] commented 1 month ago

Benchmarks summary

Performance benchmarks

aha-mont64 crc32 minver nettle-sha256 nsichneu slre statemate ud
▼ 0.418 (-0.008) 0.513 (0.000) ▼ 0.337 (-0.013) ▼ 0.655 (-0.000) ▼ 0.355 (-0.009) ▼ 0.290 (-0.003) ▼ 0.327 (-0.002) ▼ 0.433 (-0.002)

You can view all the metrics here.

Synthesis benchmarks (basic)

Device utilisation: (ECP5) LUTs used as DFF: (ECP5) LUTs used as carry: (ECP5) LUTs used as ram: (ECP5) Max clock frequency (Fmax)
▼ 23284 (-801) ▲ 5888 (+120) 802 (0) ▲ 976 (+72) ▲ 50 (+3)

Synthesis benchmarks (full)

Device utilisation: (ECP5) LUTs used as DFF: (ECP5) LUTs used as carry: (ECP5) LUTs used as ram: (ECP5) Max clock frequency (Fmax)
▼ 28112 (-4299) ▲ 9141 (+120) 1976 (0) ▲ 1156 (+72) ▲ 42 (+1)
xThaid commented 1 month ago

Branches are now resolved one cycle later, so most likely we need to flush one more instruction during an exception. Thus performance dropped.