Required some tricks. This CSR is optional to fill for all exception types, so if some case becomes too problematic in the future, it can be set to 0.
Boom and XiangShan doesn't support setting it to instruction bytes in case of Illegal Instruction, but it was added to coreblocks at currently little cost. It is helpful, because it could speed up emulation of missing instructions (possibly in OpenSBI?)
XiangShan supports setting mtval to upper half of instruction address in case of fault on misaligned instruction crossing fetch blocks, hard to tell if supported in Boom.
Other cases are handled by both processors.
Implements full
mtvalCSR.Required some tricks. This CSR is optional to fill for all exception types, so if some case becomes too problematic in the future, it can be set to 0.
Boom and XiangShan doesn't support setting it to instruction bytes in case of Illegal Instruction, but it was added to coreblocks at currently little cost. It is helpful, because it could speed up emulation of missing instructions (possibly in OpenSBI?) XiangShan supports setting mtval to upper half of instruction address in case of fault on misaligned instruction crossing fetch blocks, hard to tell if supported in Boom. Other cases are handled by both processors.