kuznia-rdzeni / coreblocks

RISC-V out-of-order core for education and research purposes
https://kuznia-rdzeni.github.io/coreblocks/
BSD 3-Clause "New" or "Revised" License
36 stars 14 forks source link

More uses of av_comb, slight refactor of RF #722

Open tilk opened 2 months ago

tilk commented 2 months ago

Probably won't change much, but here we go.

github-actions[bot] commented 2 months ago

Benchmarks summary

Performance benchmarks

aha-mont64 crc32 minver nettle-sha256 nsichneu slre statemate ud
0.417 (0.000) 0.513 (0.000) 0.337 (0.000) 0.655 (0.000) 0.361 (0.000) 0.290 (0.000) 0.326 (0.000) 0.431 (0.000)

You can view all the metrics here.

Synthesis benchmarks (basic)

Device utilisation: (ECP5) LUTs used as DFF: (ECP5) LUTs used as carry: (ECP5) LUTs used as ram: (ECP5) Max clock frequency (Fmax)
▲ 27392 (+3323) 5924 (0) 770 (0) 972 (0) ▼ 45 (-4)

Synthesis benchmarks (full)

Device utilisation: (ECP5) LUTs used as DFF: (ECP5) LUTs used as carry: (ECP5) LUTs used as ram: (ECP5) Max clock frequency (Fmax)
▼ 32284 (-1868) 9177 (0) 1944 (0) 1152 (0) ▼ 37 (-1)